Along with increasing in the number of telecommunication standards, the demand for multi-standard transmitters / receivers has been raised. The aim of this paper is to design and simulate an LNA that covers the full band of UWB and involve the available standards as well. Accordingly, the main design parameters including noise, gain, input matching, current level, and voltage level are determined so as to achieve an effective operation in the band of 3. 1 GHz to 10. 6 GHz. The proposed structure is a differential common-gate associated with the gain-boosting and current-reused techniques. Applying the proposed common-gate structure in the LNA in CMOS 0. 18μ m technology, the power consumption achieves a considerable reduction compared to other LNA counterparts. In addition, the noise figure is reduced to 1. 8dB with a gain of 12. 8 dB to 13. 6 dB, a linearity of-7dBm is achieved, and the input reflection coefficient is reduced to less than-10 dB.

In this paper, a Distributed Amplifier (DA) by using HEMT technology for ultra-wideband application is presented.Creation of Distributed integrated circuit has been investigated for approximately seventy years rapidly to developing semiconductor process technologies in the modern IC design. By using of this method, multiple parallel signals are combined and obtain to increase the bandwidth, enhanced power combining amplitude, and novel design capabilities for IC process. The circuit was designed and simulated in ED02AH technology by using ADS2010. The 4-stage design achieves 15.5 dB of power gain (± 0.5 dB) from 3.1 to 10.6 GHz. Reflected power of the input and output from loads matched to 50 Ohm are all below -10 dB over the bandwidth of the device, as is power transmitted from the output to the input. The device is stable for a wide range of input and output loads.

One of the most important parts of communication systems are matching networks. If the matching networks are not broadband, no matter how good the rest of the communication system is, the system’s bandwidth is bounded by matching network. In this project, we explain the real frequency technique and use it to design and simulate a broadband matching network for use in a broadband power amplifier. The designed prototype operates from 0. 1 up to 4 GHz with around 12 dB power gain and delivers approximately 40 dBm or 10 Watts of power. The power added efficiency of the device more than 47% in the wide operation bandwidth. CGH40010F GaN HEMT device of Wolfspeed-Cree Company is used in the design.

The Low Noise Amplifier (LNA) stands as a crucial element RF receiver chain, demanding a delicate interplay of characteristics such as high gain, low noise figure (NF), superior linearity, and an extensive dynamic range. De-signing an ultrawideband (UWB) LNA poses a complex challenge as engineers grapple with intricate trade-offs inherent in these parameters. To address these challenges, noise cancellation techniques have emerged as valuable tools, revolutionizing the design of UWB LNAs by relaxing the traditional trade-off between bandwidth and input matching. This innovative approach not only enhances bandwidth but also effectively cancels out the un-desirable noise and nonlinearities from the input MOSFET. Despite the advancements afforded by noise cancellation, the broad bandwidth of UWB LNAs presents a significant hurdle. If the linearity is insufficient, the UWB LNA faces performance degradation due to increase in-band interference. In response, this article proposes an inventive linearization technique, a combination of Noise Cancelling (NC) and complementary derivative super-position (CDS), aiming to increase the linearity of UWB LNAs. Through meticulous simulations conducted using Cadence Virtuoso with GPDK090 library, the proposed LNA showcases impressive performance metrics across the UWB spectrum. Notably, it achieves a gain ranging from 12.5 dB to 15.5 dB, a noise figure within the range of 3.9 dB to 5.26 dB, and an IIP3 spanning from 6.3 dBm to 8.8 dBm. Remarkably, this innovative LNA accomplishes these feats while operating with a modest power consumption of 11.36 mW from a 1.2 V supply. This groundbreaking technique holds promise for significantly enhancing the efficiency and overall performance of UWB LNAs within contemporary RF receiver systems.

This paper presents a new variable gain low noise amplifier (VG-LNA) for ultra-wideband (UWB) applications. The proposed VG-LNA uses a common-source (CS) with a shunt-shunt active feedback as an input stage to realize input matching and partial noise cancelling. An output stage consists of a gain-boosted CS cascode and a gain control circuit that moves the high resonant frequency to higher frequencies and provides flatness gain. The direct power gain (S21) is continuously controlled without significant degradation in the input return loss (S11) and noise figure. The proposed VG-LNA is designed and simulated using RF-TSMC 0. 18 μ m CMOS technology by Advanced Design System (ADS). Simulation results show a maximum flat power gain (S21) of 14 dB with a noise figure (NF) lower than 3. 6 dB and an input impedance matching (S11) less than – 10 dB over the wide bandwidth of 3. 5 to 13. 5 GHz. Its power consumption is 12 mW with low power supply of 0. 9 V. In addition, the power gain ranges from 7 to 14 dB at the center frequency of 8. 5 GHz.

In this paper, a wideband two-stage low-noise amplifier (LNA) is presented. The proposed architecture achieves wideband matching, low noise figure and high flat gain simultaneously by employing a negative-positive feedback technique. A common-gate input stage exploits a gm-boosting technique to achieve noise-reduction. In addition, a positive transformer feedback is used to add a degree of freedom in determining the transconductance of the impedance matching transistor. The proposed LNA has been designed and simulated using TSMC 0. 18-μ m standard RF CMOS process. Simulation results show that LNA achieves a return loss (S11) of below-10 dB, a noise figure (NF) of 2. 6– 3 dB, a flat power gain (S21) of 18± 0. 5 dB, and an IIP3 of 7 dBm, over a bandwidth of 6. 5– 10. 5 GHz. Designed LNA consumes 8 mW from a low power supply of 0. 85 V.

The most important challenges in ultra wideband Low Noise Amplifiers (LNAs) are flatness of gain, input impedance matching and lower noise figure at desired frequencies. In this paper, an ultra wideband low noise amplifier with flat gain and low noise figure at frequencies between 3. 1GHz to 10. 6 GHz is proposed. In the proposed circuit, a cascade stage is used as a main block and noise cancellation method is used for increasing gain and lowering noise figure. To have good input and output matching, active feedback is used. In addition feedback and RLC load is used for better flatness for gain of LNA. The proposed circuit is designed and simulated in TSMC 90nm CMOS Technology using HSpice simulator. Simulations show noise figure of 1. 62-2. 1dB, flat gain in the range of 11. 9-12dB and power consumption of 11. 72mW in the frequency range of 3. 1-10. 6GHz.

In this paper, a two-stage common source low noise amplifier (LNA) with novel input matching network is presented for ultra-wideband (UWB) applications. The proposed input matching network employing the active feedback and an inductive network is proposed to achieve the wideband matching, low noise figure and high flatness gain simultaneously. The proposed LNA has been designed and simulated in the RF-TSMC CMOS 0. 18 μ m technology by Advanced Design System (ADS). The simulation results exhibit a flat power gain (S21) of 15± 1 dB with a noise figure (NF) lower than 3. 5 dB and an input impedance matching less than – 10 dB over 3. 1 to 10. 6 GHz bandwidth. It consumes 10 mW from 1 V supply voltage and occupies 0. 85 mm2.

Background and Objectives: In this paper, a new design strategy was proposed in order to enhance bandwidth and efficiency of power amplifier. Methods: To realize the introduced design strategy, a power amplifier was designed using TSMC CMOS 0. 18um technology for operating in the Ka band, i. e. the frequency range of 26. 5-40GHz. To design the power amplifier, first a power divider (PD) with a very wide bandwidth, i. e. 1-40GHz, was designed to cover the whole Ka band. The designed Doherty power amplifier consisted of two different amplification paths called main and auxiliary. To amplify the signal in each of the two pathways, a cascade distributed power amplifier was used. The main reason for combining the distributed structure and cascade structure was to increase the gain and linearity of the power amplifier. Results: Measurements results for designed power divider are in good agreement with simulations results. The simulation results for the introduced structure of power amplifier indicated that the gain of proposed power amplifier at the frequency of 26-35GHz was more than 30dB. The diagram of return loss at the input and output of power amplifier in the whole Ka band was less than-8dB. The maximum Power Added Efficiency (PAE) of the designed power amplifier was 80%. The output P1dB of the introduced structure was 36dB, and the output power of power amplifier was 36dBm. Finally, the IP3 value of power amplifier was about 17dB. Conclusion: The strategy presented in this paper is based on usage of Doherty and distributed structures and a new wideband power divider to benefit from their advantages simultaneously.